Using Variables to make a Simpler Makefile

Hopefully during your student career you are going to develop a really large program... Files often change, and having to check every line of your make file to add and delete new files can be a nightmare!

For this reason we use variables on Makefiles.

Here is a rewrite of the Makefile for Lab04 Step 4:

CC = g++                      # for the compiler we are going to use                                             
CFLAGS = -c -g -Wall          # to keep the options I want to pass to the compiler
DEPS = functions.h
LDFLAGS =                     # hmm: What might this Macro be used for?                                                         
SOURCES = main.cpp functions.cpp
OBJECTS = $(SOURCES:.cpp=.o)  # means copy .cpp names to .o names ;-)
EXECUTABLE = hello            # for the executable program's name                                                

all: $(SOURCES) $(EXECUTABLE) 

$(EXECUTABLE) : $(OBJECTS) 
        $(CC) $(LDFLAGS) $(OBJECTS) -o $@ 

main.o : main.cpp functions.h 
	$(CC) $(CFLAGS) main.cpp 

functions.o : functions.cpp functions.h 
        $(CC) $(CFLAGS) functions.cpp 

clean: 
        rm $(EXECUTABLE) $(OBJECTS)

Ok much better... One of your homework questions contains an even more powerful makefile.

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Prepared by Stratos Dimopoulos.