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12.1 Debugging Features of the Architecture

The features of the 80386 architecture that support debugging include:

Reserved debug interrupt vector: Permits processor to automatically invoke a debugger task or procedure when an event occurs that is of interest to the debugger.
Four debug address registers: Permit programmers to specify up to four addresses that the CPU will automatically monitor.
Debug control register: Allows programmers to selectively enable various debug conditions associated with the four debug addresses.
Debug status register: Helps debugger identify condition that caused debug exception.
Trap bit of TSS (T-bit): Permits monitoring of task switches.
Resume flag (RF) of flags register: Allows an instruction to be restarted after a debug exception without immediately causing another debug exception due to the same condition.
Single-step flag (TF): Allows complete monitoring of program flow by specifying whether the CPU should cause a debug exception with the execution of every instruction.
Breakpoint instruction: Permits debugger intervention at any point in program execution and aids debugging of debugger programs.
Reserved interrupt vector for breakpoint exception: Permits processor to automatically invoke a handler task or procedure upon encountering a breakpoint instruction.

These features make it possible to invoke a debugger that is either a separate task or a procedure in the context of the current task. The debugger can be invoked under any of the following kinds of conditions:

Task switch to a specific task.
Execution of the breakpoint instruction.
Execution of every instruction.
Execution of any instruction at a given address.
Read or write of a byte, word, or doubleword at any specified address.
Write to a byte, word, or doubleword at any specified address.
Attempt to change a debug register.

up: Chapter 12 -- Debugging
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next: 12.2 Debug Registers